Room 102A
Title: Developing HPC accelerators using SDAccel for Xilinx FPGAs on-premise or in-cloud
Presenters: Parimal Patel, XUP Senior Systems Engineer
Abstract: High-Performance Computing (HPC) applications are pushing the adoption of accelerated computing based on heterogeneous architectures into mainstream, as traditional CPU technology is unable to keep pace. FPGA accelerators complement CPU-based architectures and deliver significant performance and power efficiency improvements. In this regard, Xilinx FPGAs are available on the Amazon Elastic Compute Cloud (EC2) as F1 instances and on- premise as Alveo cards, which are designed to accelerate data center and HPC workloads. The SDAccelTM Development Environment enablesthe user to easily and productively develop accelerated algorithms and then efficiently implement and deploy them onto the heterogeneous CPU-FPGA system both in cloud and on-premise environments. SDAccel offers the possibility to specify a compute kernel using C and C++ for higher-level algorithmic implementation, or using hardware description languages for RTL designs, while using OpenCL APIs to control run-time behavior. The high performance and high-level of scalability offered by F1 instances, paired with the power and ease of use of Xilinx SDAccel, is very appealing for the development of high high-performance FPGA- based accelerated solutions, and will be the focus of this workshop.
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